Thursday, January 24, 2008

ATMEGA88 Teardown

An 8k FLASH, 512 bytes EEPROM, 512 bytes SRAM CPU operating 1:1 with the external world unlike those Microchip PIC's we love to write up about :).

It's a 350 nanometer (nm), 3 metal layer device fabricated in a CMOS process.  It's beautiful to say the least;  We've torn it down and thought we'd blog about it!

[Note:  Clicking on pictures will give you a large ~13 MB file]

The process Atmel uses on their .35 micrometer (um) technology is awesome.  The picture above is 200x magnified of the die (aka the substrate).


Using a little HydroFluoric Acid (HF) and we partially removed the top metal layer (M3).  Everything is now clearly visible for our analysis.

After delaying earlier above, we can now recognize features that were otherwise hidden such as the Static RAM (SRAM) and the 32 working registers.

As we mentioned earlier, we used the word, "awesome" because check this out- It's so beautifully layed out that we can etch off just enough of the top metal layer to leave it's residue so it's still visible depending on the focal point of the microscope!  This is very important.  See the pictures below to better understand.

The pictures above and below are the same pictures with the exception that the lower picture has M3 removed but the trough in the SIO2 remains (e.g. the layer has not been completely etched off). 

Can you see why we said Atmel's process is awesome?  We removed obscuring metal but can still see where it went (woot!).


The two photos above contain two of the 30+ configuration fuses present however it makes a person wonder why did Atmel cover the floating gate of the upper fuse with a plate of metal (remember the microchip article with the plates over the floating gates?)

 We highlighted a track per fuse in the above photos.  What do you think these red tracks might represent?

Tuesday, January 22, 2008

Security Mechanism of PIC16C558,620,621,622

Last month we talked about the structure of an AND-gate layed out in Silicon CMOS.  Now, we present to you how this AND gate has been used in Microchip PICs such as PIC16C558, PIC16C620, PIC16C621, PIC16C622, and a variety of others.

If you wish to determine if this article relates to a particular PIC you may be in possession of, you can take an windowed OTP part (/JW) and set the lock-bits.  If after 10 minutes in UV, it still says it's locked, this article applies to your PIC. 


The picture above is the die of the PIC16C558 magnified 100x.  The PIC16C620-622 look pretty much the same.  If there are letters after the final number, the die will be most likely, "shrunk" (e.g. PIC16C622 vs PIC16C622A). 

Our area of concern is highlighted above along with a zoom of the area.  

When magnified 500x, things become clear.  Notice the top metal (M2) is covering our DUAL 2-Input AND gate in the red box above.

We previously showed you one half of the above area.  Now you can see that there is a pair of 2-input AND gates.  This was done to offer two security lock-bits for memory regions (read the datasheet on special features of the CPU).

Stripping off that top metal (M2) now clearly shows us the bussing from two different areas to keep the part secure.  Microchip went the extra step of covering the floating gate of the main easilly discoverable fuses with metal to prevent UV from erasing a locked state.  The outputs of those two fuses also feed into logic on the left side of the picture to tell you that the part is locked during a device readback of the configuration fuses.

This type of fuse is protected by multiple set fuses of which only some are UV-erasable.  The AND gates are ensuring all fuses are erased to a '1' to "unlock" the device.

What does this mean to an attacker?  It means, go after the final AND gate if you want to forcefully unlock the CPU.  The outputs of the final AND gate stage run underneather VDD!! (The big mistake Microchip made).  Two shots witha laser-cutter and we can short the output stages "Y" from the AND-gate to a logic '1' allowing readback of the memories (the part will still say it is locked). 

Stripping off the lower metal layer (M1) reveils the Poly-silicon layer.

What have we learned from all this?

  • A lot of time and effort went into the design of this series of security mechanisms.

  • These are the most secure Microchip PICs of ALL currently available.  The latest ~350-400nm 3-4 metal layer PICs are less secure than these.

  • Anything made by human can be torn down by human!